SoC Test Scheduling using Simulated Annealing Algorithm

• Main Authors: Chen-Fu Huang, 黃晨富
• Other Authors: Trong-Yen Lee
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/76519178111171109290

碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 92 === As the semiconductor technology has made great progress, System-on-a-Chip (SoC) has become the kernel technologies for integrating computer, consumer, and communication. Test scheduling is an important problem in SoC test automation. In this paper, we propose a SoC test scheduling method which is based on simulated annealing algorithm. A data structure, called a sequence pair, is used to represent the placement of rectangles, because the scheduling is formulated as a two-dimensional bin packing problem. We also consider power consumption restriction and reduce idle time in SoC test scheduling. Experiments are conducted on ITC’02 benchmarks. Experiment results show our proposed method is efficiently and the test time is shorter than earlier methods about 3% ~ 24%.