THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT

THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT

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碩士 === 大同大學 === 電機工程研究所 === 92 === Based on the phase-locked-loop (PLL) design concepts, this thesis presented the designs of a RF frequency synthesizer with a LC-tank voltage-controlled oscillator and a clock and data recovery (CDR) circuit with a ring oscillator. The implementation of the frequenc...

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Main Authors: Chang-Ping Chang, 張璋平
Other Authors: Shu-Chuan Huang
Format: Others
Language:en_US
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/28096944749099077239
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spelling ndltd-TW-092TTU004420302016-06-15T04:17:09Z http://ndltd.ncl.edu.tw/handle/28096944749099077239 THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT 鎖相迴路架構的頻率合成器與資料回復器設計 Chang-Ping Chang 張璋平 碩士 大同大學 電機工程研究所 92 Based on the phase-locked-loop (PLL) design concepts, this thesis presented the designs of a RF frequency synthesizer with a LC-tank voltage-controlled oscillator and a clock and data recovery (CDR) circuit with a ring oscillator. The implementation of the frequency synthesizer for 802.11a includes the building blocks such as the phase frequency detector, charge pump, loop filter and prescaler. A high-speed prescaler is designed based on injection-locked and Miller frequency dividers. The implementation of the CDR circuit for 2.488GHz optical communications is also presented. The building blocks of CDR that including phase detector, charge pump, loop filter and VCO are discussed and designed. The circuits are simulated with simulink and ADS to verify the system- and transistor- level performances based on TSMC 0.18um CMOS one-poly six-metal (1P6M) technology with a 1.8V supply. Shu-Chuan Huang 黃 淑 絹 2004 學位論文 ; thesis 91 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 大同大學 === 電機工程研究所 === 92 === Based on the phase-locked-loop (PLL) design concepts, this thesis presented the designs of a RF frequency synthesizer with a LC-tank voltage-controlled oscillator and a clock and data recovery (CDR) circuit with a ring oscillator. The implementation of the frequency synthesizer for 802.11a includes the building blocks such as the phase frequency detector, charge pump, loop filter and prescaler. A high-speed prescaler is designed based on injection-locked and Miller frequency dividers. The implementation of the CDR circuit for 2.488GHz optical communications is also presented. The building blocks of CDR that including phase detector, charge pump, loop filter and VCO are discussed and designed. The circuits are simulated with simulink and ADS to verify the system- and transistor- level performances based on TSMC 0.18um CMOS one-poly six-metal (1P6M) technology with a 1.8V supply.
author2 Shu-Chuan Huang
author_facet Shu-Chuan Huang
Chang-Ping Chang
張璋平
author Chang-Ping Chang
張璋平
spellingShingle Chang-Ping Chang
張璋平
THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
author_sort Chang-Ping Chang
title THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
title_short THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
title_full THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
title_fullStr THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
title_full_unstemmed THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
title_sort design of pll-based frequency synthesizer and clock/data recovery circuit
publishDate 2004
url http://ndltd.ncl.edu.tw/handle/28096944749099077239
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