| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 92 === A typical co-design environment has a number of component processes assigned for execution either in hardware or in software. These components have an obvious interaction requirement in order to meet the system functionality. Reuse of Intellectual Property (IP) is crucial in SoC design. The discrepancies in interface logic and communication/bus protocols among IPs, however, remain as the main obstacle in system integration. In this paper, we examine the interface logic generation problem and propose a novel scheme to automate the process. The scheme consists of an automatic communication / bus protocol translation and a template based interface logic / bus wrapper generation. Real case test bench, e.g. AHB in AMBA v.s. BVCI in VCI was applied to verify the correctness and the efficiency of the generated interface. The design is also implemented in FPGA and incurred interface circuitry overhead is small.
|
|---|
