Zero Skew Clock Tree Synthesis
碩士 === 逢甲大學 === 資訊工程所 === 93 === As the process progress, there are more and more modules in a single chip. As for this reason, the designs are more and more advanced. But there are some problem never happen before will appear, such as power consumption, signal integrity, clock issue and so on. B...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14350010607464139294 |