A 1.8V 10b 135MSPS Two-Step ADC in 0.18um CMOS

• Main Authors: Shing-Ming Yen, 嚴祥銘
• Other Authors: Ching-Chun Wang
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/49637633361301991239

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === 　Digital video applications, such as HDTV, digital camera, communication, and medical imaging system require various system architectures and circuits for signal processing. Among these, A/D converters are key components in analog signal processing, and require conversion speed 100MS/s ~ 200MS/s, resolution 8~12 bit. This thesis describes a 1.8V, 10-bit, 135MS/s A/D converter suitable for video applications. The proposed A/D converter is designed with a two-step architecture and is divided into two primary components, a 6-bit coarse converter and a 5-bit fine converter. The two-step ADC with interleaved fine conversions achieves 9.217bits with a sampling frequency of 135Mhz and a sinusoidal input signal of 25.18066406MHz frequency simulation. The A/D converter is implemented with TSMC 1P6M 0.18um mixed-signal process. The chip power consumption is 108mW at 1.8V power supply and area including pads is 1.8*2.3mm2.