| Summary: | 碩士 === 國立成功大學 === 電腦與通信工程研究所 === 93 === This thesis addresses the design of a TCP/IP hardware module which can be used in an SoC system or an enhanced Network Interface Controller (NIC). The present implementation uses a state machine-based design which performs limited TCP/IP functions along with the required firmware for data movement and buffer management. There are several features of this design.
1.Three main functions：Ping request/ reply, UDP connection, and TCP connection management.
2.Header processing modules for ARP, IP, ICMP, UDP, and TCP protocols are implemented in hardware.
3.The design is capable for 8 concurrent UDP/ TCP connection management.
4.A bypass circuit is used to handle the IP header checksum and layer 4 checksum, including verification for receiving
datagrams and checksum calculation for transmitted datagram.
However, at the time of writing this thesis, the implementation is not fully accomplished. The design of the whole Offload Engine is implemented except for the layer 4 processing modules. An SoC system is made by the Altera PCI Development Kit to test the Offload Engine. The performance estimation shows that the system can process 100Mps network packets in wire-speed if the clock rate is greater than 14.7 MHz. The timing analysis shows that the clock rate of the implementation can be set to 49MHz.
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