| Summary: | 碩士 === 國立成功大學 === 電腦與通信工程研究所 === 93 === The Instruction Set Architecture (ISA) of a microprocessor inside a SoC system is an important design decision because the feature of the ISA dominates the overall performance of the system. It is critical to understand how efficient a program can be executed on different ISAs. In this thesis, a Dual-ISA microprocessor is proposed to accommodate the need of evaluating two different ISAs with one core.
Two ISAs, namely ARMv4 and MIPS32 are chosen to be the implementation target of this thesis. A novel architecture called ”Dual Core with Shared Resources(DCSR)” is also proposed。A CPU core supporting ARMv4 ISA is implemented as the baseline since the ARMv4 ISA is more complex than MIPS32. Based on this CPU core, the ARMIPS32 CPU core is developed by modifying the ARM core to support MIPS32 ISA. ARMIPS32 can support ARMv4/MIPS32 Dual-ISA with only 24K extra logic gates, and retain the same clock rate of the ARM CPU Core.
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