| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 93 === This thesis introduces the software implementation of the IEEE 802.16a TDD uplink transceiver system. We integrate the FEC encoder in the transmitter, the synchronizer, the channel equalizer, and the FEC decoder in the receiver.
We first do some modifications to the uplink synchronization algorithm, and then optimize our programs on the digital signal processing (DSP) platform, which includes a personal computer (PC), Innovative Integration’s Quixote DSP board, and the TI’s TMS320C6416 DSP chip.
The uplink synchronization mechanism is using the invariance of the preamble which is also known to the base station. We correlate it to the received signals directly, and thus find the first coming subscriber station’s time to reduce the inter-symbol interference.
The data formats on this system are all “fixed-point” for improving the computational efficiency in DSP. Our optimization goal is to accelerate the program’s execution speed so that it can satisfy the requirement of real-time processing. We present some optimization techniques, such as software pipelining, and using the intrinsics of DSP, to deal with the most time-consuming parts of the program. We also discuss and analyze the compiler feedbacks to understand how the program works in the DSP.
Finally, the speed of the interpolator filter in the transmitter and the uplink synchronizer in the receiver can be improved by 85.58 and 1.74 times, respectively. The computational efficiencies of them are 90.94% and 85.87%, respectively.
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