| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 93 === This thesis presents the design of high speed frequency dividers and quadrature voltage controlled oscillators. First, we use GCT 2.0 um InGap/GaAs HBT and TSMC 0.35μm SiGe BiCMOS processes to implement the two kinds of circuits. In frequency divider circuits, have implemented several structures as follower：(1)Static frequency divider can operate from 2 to 7.4GHz. (2)Dynamic frequency divider can operate from 2 to 11GHz. (3)Superdynamic frequency divider can operate from 6 to 9.7GHz. (4)Injection locked frequency divider can operate from 9.636 to 10.246GHz. (5)Regenerative frequency divider can operate from 7 to 27GHz, and (6)Dual modulus frequency divider(÷4/5) can operate from 0.25 to 3.8GHz. Those circuits have particular characteristics and can be chosen to fit the specs of the system. The detail expansions will be discussed in the following chapters. Also, the realization of top-series and superharmonic coupling quadrature VCOs are shown in this thesis. One has a better phase noise than the other, but a worse phase error than the other. Each topology can be used in a transceiver that has different requirements of phase noise and phase error. Finally, a new structure of VCO is presented. Depending on the theories and simulations, the performance of the circuit might be better than the others.
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