Design and Implementation of a SOVA-based W-CDMA Turbo Decoder
碩士 === 國立清華大學 === 電機工程學系 === 93 === In recent years, as the result of rapid growing of the technology in mobile communication, the data transmission rate is promoting unceasingly. For example, the maximum data rate of W-CDMA in 3GPP spec is already up to 2 Mbps. To ensure the better quality of trans...
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ndltd-TW-093NTHU54420432016-06-06T04:11:35Z http://ndltd.ncl.edu.tw/handle/61731917970918345155 Design and Implementation of a SOVA-based W-CDMA Turbo Decoder 以SOVA為主體W-CDMA渦輪解碼器之研製 Yang-Chih Lin 林揚智 碩士 國立清華大學 電機工程學系 93 In recent years, as the result of rapid growing of the technology in mobile communication, the data transmission rate is promoting unceasingly. For example, the maximum data rate of W-CDMA in 3GPP spec is already up to 2 Mbps. To ensure the better quality of transmission at high speed, the channel encoding/decoding becomes a key issue. The main problem is how to get the low bit error rate and high decoding rate at the same time. For the former issue, the outstanding decoding ability of turbo code-- nearly approaching the Shannon limit-- has made it the widely accepted choice for use in mobile communication. But for the latter issue, there are still challenges in hardware design for turbo decoding. Tradeoffs must be made carefully between the decoding algorithm, hardware complexity, performance and decoding speed. In this thesis, the focus is on the design and implementation of a turbo decoder complying with the W-CDMA spec. Firstly, the W-CDMA interleaver needed in the encoding/decoding process is discussed and a hardware architecture for its implementation is proposed. Then the design of the turbo decoder is considered. SOVA is the primary decoding algorithm adopted in the thesis. In particular, the Two-Step SOVA architecture is adopted because of its low complexity. Moreover, the entire design flow of the hardware architecture and the details of each module of the SOVA decoder will be discussed. In order to compensate the congenital flaw of SOVA, we proposed some approaches to lower the BER by fixing the scaling factor of the channel and by using max* in the ACSU (Add & Compare and Select Unit) instead of max module in our design. We also added an iteration termination module in the decoder to increase the whole decoding speed. The “optimal” values of pertinent parameters of the decoder, such as the iteration times, quantization levels, the scaling factor of the channel,.., etc. are first obtained by software simulation and then used in the subsequent hardware design. Finally, a PCI-based FPGA platform is utilized to verify the circuit performance of our design. Via PCI interface, a PC can transmit the channel noise corrupted data source to the SOVA turbo decoder implemented on the FPGA and receive its decoded results, and plots the BER vs. SNR. The experimental results show that the decoding rate of our design can achieve above 3 Mbps when the FPGA is operating at approximately 40 MHz. Tai-Lang Jong Yuan-Tzu Ting 鐘太郎 丁原梓 2005 學位論文 ; thesis 70 zh-TW |
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碩士 === 國立清華大學 === 電機工程學系 === 93 === In recent years, as the result of rapid growing of the technology in mobile communication, the data transmission rate is promoting unceasingly. For example, the maximum data rate of W-CDMA in 3GPP spec is already up to 2 Mbps. To ensure the better quality of transmission at high speed, the channel encoding/decoding becomes a key issue. The main problem is how to get the low bit error rate and high decoding rate at the same time. For the former issue, the outstanding decoding ability of turbo code-- nearly approaching the Shannon limit-- has made it the widely accepted choice for use in mobile communication. But for the latter issue, there are still challenges in hardware design for turbo decoding. Tradeoffs must be made carefully between the decoding algorithm, hardware complexity, performance and decoding speed.
In this thesis, the focus is on the design and implementation of a turbo decoder complying with the W-CDMA spec. Firstly, the W-CDMA interleaver needed in the encoding/decoding process is discussed and a hardware architecture for its implementation is proposed. Then the design of the turbo decoder is considered. SOVA is the primary decoding algorithm adopted in the thesis. In particular, the Two-Step SOVA architecture is adopted because of its low complexity. Moreover, the entire design flow of the hardware architecture and the details of each module of the SOVA decoder will be discussed. In order to compensate the congenital flaw of SOVA, we proposed some approaches to lower the BER by fixing the scaling factor of the channel and by using max* in the ACSU (Add & Compare and Select Unit) instead of max module in our design. We also added an iteration termination module in the decoder to increase the whole decoding speed. The “optimal” values of pertinent parameters of the decoder, such as the iteration times, quantization levels, the scaling factor of the channel,.., etc. are first obtained by software simulation and then used in the subsequent hardware design. Finally, a PCI-based FPGA platform is utilized to verify the circuit performance of our design. Via PCI interface, a PC can transmit the channel noise corrupted data source to the SOVA turbo decoder implemented on the FPGA and receive its decoded results, and plots the BER vs. SNR. The experimental results show that the decoding rate of our design can achieve above 3 Mbps when the FPGA is operating at approximately 40 MHz.
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author2 |
Tai-Lang Jong |
author_facet |
Tai-Lang Jong Yang-Chih Lin 林揚智 |
author |
Yang-Chih Lin 林揚智 |
spellingShingle |
Yang-Chih Lin 林揚智 Design and Implementation of a SOVA-based W-CDMA Turbo Decoder |
author_sort |
Yang-Chih Lin |
title |
Design and Implementation of a SOVA-based W-CDMA Turbo Decoder |
title_short |
Design and Implementation of a SOVA-based W-CDMA Turbo Decoder |
title_full |
Design and Implementation of a SOVA-based W-CDMA Turbo Decoder |
title_fullStr |
Design and Implementation of a SOVA-based W-CDMA Turbo Decoder |
title_full_unstemmed |
Design and Implementation of a SOVA-based W-CDMA Turbo Decoder |
title_sort |
design and implementation of a sova-based w-cdma turbo decoder |
publishDate |
2005 |
url |
http://ndltd.ncl.edu.tw/handle/61731917970918345155 |
work_keys_str_mv |
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