Jitter Performance Study For Phase-Lock Loop

• Main Authors: Yu-Chen Chiang, 江宇晟
• Other Authors: Po-Chiun Huang
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/70476321354403064487

碩士 === 國立清華大學 === 電機工程學系 === 93 === In many circuits, PLL must provide an output clock to follow the input clock closely. Examples of applications that use PLL include clock and data recovery, clock synthesis, and synchronization, frequency synthesis and PLL modulator or de-modulator application. As environment clock speed rise up, the jitter performance for PLL is more and more important. The jitter source of PLL comes from many no ideal effect of PLL, such as power supply noise, substrate noise, VCO noise, and charge pump current mismatch. This thesis proposes the prediction method of jitter performance, for estimate the output jitter comes from each noise source. Initially, Hspice and Spectre are used to estimate the output phase noise of each noise source in coordinate with phase-noise-to-jitter transfer function and noise transfer function (NTF) to estimate the PLL output jitter. This thesis primary considered the noise created by phase-locked loop. Include thermal analysis and the phase noise created by each block in PLL. Thermal Analysis: This part primarily analysis the phase noise created by each block in PLL. Then use the phase noise to jitter equation to estimate the PLL output jitter. PLL Each Block Phase Noise: This park primarily consider VCO phase noise、current mismatch created by PFD/CP and input clock phase noise.