A WCDMA/HSDPA Baseband Transceiver

• Main Authors: Chien-Jen Huang, 黃建人
• Other Authors: Hsi-Pin Ma
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/31212587848234169235

碩士 === 國立清華大學 === 電機工程學系 === 93 === In this thesis, WCDMA communication systems and HSDPA systems are presented. Then, we propose a baseband transceiver architecture for HSDPA communication systems and its circuit design. In order to improve the transmission data rate in downlink WCDMA communication systems, 3GPP has proposed HSDPA communication systems in Release 4 and Release 5 documents. After system specification description, a baseband transceiver for HSDPA communication systems is proposed. In this proposed transceiver, we focus on receiver design. We use Common Pilot Channel (CPICH) to achieve channel estimation and restore High-Speed Share Control Channel (HS-SCCH) and High-Speed Physical Downlink Share Channel (HS-PDSCH) data. Receiver can mainly be divided into four parts: synchronization, equalization, de-spreading and symbol recovery. The synchronization part includes a channel estimator, a carrier frequency synchronization, and a timing synchronization. In channel estimator, the multiple-dwell detection is introduced to minimize the size and power consumption of matched filter. Besides, applicable algorithms is adopted to design the frequency synchronization loop, timing synchronization loop, and adaptive equalizer base on low cost and practical criterion but without losing performance even better. The detail architecture and algorithm of each reception technique in receiver will be presented in the thesis. After system functional simulation based on propagation conditions of multi-path Doppler fading environment in 3GPP for HSDPA with carrier frequency and timing offset inserted, the circuit design of the proposed HSDPA transceiver will be mentioned. Matched filter and time domain LMS equalizer are the dominant components in receiver. Via coarse comparison and evaluation of the hardware cost and computation complexity, hardware reduction from modified detection algorithm and the emphasis of hardware implementation of whole receiver can be addressed clearly. Finally, some future works and the conclusions of this thesis will be given.