| Summary: | 碩士 === 國立清華大學 === 通訊工程研究所 === 93 === In this paper low-density parity-check (LDPC) codes are investigated. The performance of these randomly and deterministically constructed codes in terms of the bit error rate is compared, where the block lengths of interest are between 1000 and 10000. These block lengths are suitable for practical applications. The convergence behavior of the decoding process using the iterative sum-product algorithm is analyzed for these finite length LDPC codes. The decoding process is visualized by animations of the evolution of the messages passed in the decoder. With these visualizations, successful decoding as well as decoding errors are investigated.
Then it will be discussed in implementing the graph encoder and decoder for low density parity check codes into an hardware component. Advanced decoding signal processing algorithms and systems architectures which enable low complexity and fast decoding solutions will be developed. For an efficient and fast implementation methodology, a fully parallel decoder architecture is proposed which is expected to enhance the throughput of the overall system dramatically.
Finally, I try to combine the LDPC codes with the multimode fiber transmission system, and analyze the associated performance result.
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