| Summary: | 碩士 === 國立臺灣海洋大學 === 電機工程學系 === 93 === Image segmentation is an important class of techniques critical to many applications requiring image processing, such as computer vision, image recognition, biomedicine, remote sensing, object-based video coding, etc. Region growing and merging is a well-established segmentation method that can be used with most image types. In general, this method first divides the image into many small regions and then gradually merges the small regions into larger regions according to some criteria for homogeneity. Obviously, this is a computation intense process and, since watershed algorithm belongs to this category of segmentation methods, it is inherently computation intense as well. Keeping this in mind, we develop in this study a hardware structure to accelerate the region growing process within the execution flow of the watershed algorithm. The main idea is to use redundant hardware to compute the eight nearest neighbors at the same time for a given pixel. On the other hand, the hardware cost is greatly reduced by using only one FIFO queue to store the pixels that represent the potential catchment basin members. Our design process starts from writing a C code to verify the algorithm which is modified from the one proposed by Meyer. A synthesizable RTL code in Verilog HDL is then developed and the circuit synthesized to Xilinx Spartan 3E device. The clock rate of the circuit obtained reaches 75 MHz.
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