| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 93 === In the recent decade, voltage scaling has become an attractive feature for many system component designs. With this feature, the system components could reduce their energy consumption dramatically by adjusting their supply voltages and clock rates dynamically. In this thesis, we consider energy-efficient real-time task scheduling over a chip multiprocessor architecture with the capability of voltage scaling, in which multiple cores are equipped on a single chip. The objective is to schedule a set of frame-based tasks with the minimum energy consumption, where all tasks are ready at time 0 and share a common deadline. With the deep sleeping property that some optimal schedules satisfy, we can derive an optimal schedule when a task assignment is given. We show that such a minimization problem is NP-hard by the insight of how to derive an optimal schedule. We adopt the Largest-Task-First strategy to derive a feasible schedule and then prove the proposed algorithm has a 2.371-approximation ratio for this problem. The strength of the proposed algorithm was demonstrated by a series of simulations, for which near optimal results were obtained.
|
|---|
