| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === This thesis presents the design and implements the analog baseband for 802.11a/b/g WLAN direct-conversion receiver architecture in UMC 0.18um CMOS process. The whole baseband function is verified by two chips. One is the seventh-order chebyshev channel selection filter, and the other is the automatic frequency tuning loop.
The filter type of the seventh-order chebyshev channel selection filter is active-rc, and cascade method is applied to implement this high-order filter. The filter itself can switch the gain-level and bandwidth for different WLAN standards. Servo-loop in the filter can solve the issue of dc-offset. According to measurement results, the gain level of the filter is form 20dB to 60dB in 10dB steps. The f3dB for different operating bandwidth are 7.56MHz, 19.5MHz, and 26.5MHz. Besides, the noise and linearity are analyzed for different operating bandwidth. The die area is 1.15*1.45 mm2 and the power consumption is 22.248mW.
Automatic frequency tuning loop is used for solving the inaccuracy of the active filter bandwidth. It is implemented in the master-slave method. The cap array values of the filter are determined by the binary-search to self-calibrate the filter bandwidth. In order to verify the function of the ATL, we apply second-order biquad as the slave filter. According to the measurement results, the calibration frequency range is from 4.3MHz to 11.34MHz. The die area is 1.5*1.33mm2, and the power consumption is 10.8mW.
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