| Summary: | 博士 === 國立臺灣大學 === 電子工程學研究所 === 93 === An adaptive equalizer plays a key role at the receiver in modern digital transmission systems. The design of this equalizer is important since it determines the transmission quality attainable. Also, the equalizer occupies a high portion of the computational complexity in implementing the demodulator. Theses properties have made it the focus of much analytical and practical design. Recently, many researches of interest in communication systems are to increase transmission rate and recording density. However, with the increase of transmission rate and recording density, the signals propagating the channel suffer from serious channel distortion, which causes intersymbol interference (ISI). Hence, to design a robust and high-speed equalizer becomes important and necessary.
A decision feedback equalizer (DFE) is an efficient scheme to suppress this ISI. However, most cost-effective DFE implementations suffer from the phenomenon of error propagation, which degrades system performance in the sense of bit error rate (BER) or signal-to-noise ratio (SNR). In this thesis, we propose a soft-threshold-based multi-layer DFE (STM-DFE) algorithm to suppress the error propagation. Simulation results show that the proposed STM-Algorithm can efficiently reduce the BER and burst error length (BEL). When being applied to a practical Lorentzian channel and channels of different eigenvalue spread, the STM algorithm even outperforms the ideal DFE (IDFE) system (in an IDFE, symbols are assumed to be correctly fed back without propagation errors).
In VLSI implementations of the STM-DFE, the hardware overhead is negligible compared with a conventional DFE. The direct implementation can be applied to low-speed application such as magnetic data storage systems. In addition, for high-speed applications, we propose a two-stage precomputation scheme to lower the hardware overhead. A new adaptive algorithm to update for a DFE with precomputation scheme is also proposed so that both hardware complexity and power consumption can be saved. Finally, we consider the application of the STM-DFE to 10GBase-LX4 systems. With the help of the STM-DFE, we can perform effective EQ, and the required bit number of ADC can be reduced from 8 to 6. That is, STM-DFE can help to ease the ADC precision requirement, and help to save the silicon cost in implementing the receiver ICs.
|
|---|
