| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 93 === The disabled people such as arm amputees or spinal cord injured patients usually need to use assistive devices like electric prosthesis or functional electrical stimulation system. It is an important topic to control these devices. EMG signal is one of the feasible control commands extensively investigated in many researches. An FPGA-based EMG recognition system is developed in this thesis. Most of core algorithms are derived from the previous researches of our laboratory.
Two sets of active electrode are bilaterally placed on the triangular region surrounded by the sternocleidomastoid, the upper trapezius, and the clavicle to collect surface EMG signals. Five motions of neck and shoulders are specified to provide possible control commands. The integrated EMG is computed to detect the onset of muscle contraction. The cepstral parameters derived from autoregressive coefficients are used as the recognition features. The autoregressive coefficients can be calculated by using the estimated autocorrelation lags in the Yule-walker equation. These features are then discriminated using the dynamic timing warping (DTW) method.
There are three parts in our hardware architecture including autocorrelation module, feature extraction module, and classifier module. The feature parameters from individual channel are concatenated to form a feature vector for classification. Two channels of EMG signal must be processed simultaneously. The data rate requirement of EMG signal processing is much lower than the clock rate of our chip design. To avoid rapid growth of logic units due to circuit duplication, we reduced the hardware functional units by time-multiplexing several operations such as multiplication and addition in algorithm. A design with small area and low cost can be achieved with the multiplexing controlled by a finite state machine (FSM). A single multiplication-and-accumulation (MAC) unit is shared to calculate Hamming window and autocorrelation functions of both two channels. There are several divisions used in Levinson-Durbin algorithm. A software solution usually needs a microprocessor to perform division; besides, it takes many clock cycles to complete a division, which is obviously not a good choice in our architecture. A sequential divider using subtract-and-shift algorithm is implemented in our design. After observing the operation flow of dynamic timing warping method, we establish some rules to reduce the amount of registers extensively. One subtractor is shared to calculate the distance between test and reference feature vectors. The final design is downloaded and verified on Altera Stratix FPGA. The simulation results show that the clock rate is 35MHz clock rate and the hardware requirement is 4379 logic elements.
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