| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 93 === In communication system, turbo decoder is widely used nowaday. However, the specifications of turbo decoders are difference in various communication applications. It will cost lot of time and labor to design turbo decoder with traditional methods, which does not meet Time to Market requirement. In this thesis, we propose a De-interleaver free table turbo decoder SIP generator. This IP generator not only provides IC designer to generate a turbo decoder with configurable parameter but also the automatic performance simulation which produces the SNR and BER relation charts for IC designers to evaluate the error correction efficiency. Moreover, we analyzed the characteristics of interleaver and de-interleaver then re-arranged the extrinsic memory access order; thus only one interleaver table is needed to perform the function of interleaver and de-interleaver. This new architecture effectively reduces the extrinsic memory to half and shrinks the chip area and lowers the power consumption. Finally as to verify our SIP generator, we have synthesized the turbo decoder chips which consist 1, 2, and 4 parallel MAP decoders by TSMC 0.18 1p6m process, and also performed efficiency analysis. The experimental results show that the memory area is reduced by 9.5%~15.6% and power consumption by 5.7%~11.11% without degrading the decoding speed.
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