IC Design of a Decision Device for Analog Viterbi Decoder

• Main Authors: Ming-Jiun Liu, 呂銘峻
• Other Authors: 李文達
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/rye8an

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 93 === In transitional implementation of wireless communication, it is essential to use a high-speed and high-resolution A/D converter when the receiver signal gets into the digital demodulator and channel decoder. In this paper, we present a new structure that can process the demodulation without A/D converter. In our method, we have designed an analog decision device using QAM demodulator. Meanwhile, to verify our method, we have also finished a front-end analog Viterbi decoder circuit. Finally, we have designed one analog decision chip and one front-end analog Viterbi decoder chip with UMC 0.18-μm 1P6M CMOS technology. In the decision device chip, it contains 494 transistors, operates to 100Mb/s using a single 3.3-V power supply and consumes 17.46mW. The chip area of the analog decision is about 0.544mm2 . The front-end analog Viterbi decoder chip contains 164 transistors, operates to 100MHz using a single 3.3-V power supply and consumes 22.2mW. The chip area of the analog decision is about 0.286mm2. These chips have the advantages of low-power, small-area, low-cost and are easy to be combined with the RF Front-End Receiver. The new architecture can provide an efficient design for future SOC communications.