| Summary: | 碩士 === 淡江大學 === 電機工程學系碩士班 === 93 === In the applications for the modern communication and wireless network systems, the analog-to-digital (A/D) converters play an important role in the systems. The over-sampling and noise shaping techniques are used in analog to digital conversion interface of modern very-large-scaled integrated circuits. Due to over-sampling characteristics, the delta sigma (ΔΣ) modulators usually are limited on the application of voice band signals. As the integrated circuits process improvement, it makes many researches transfer to applications of wide-bandwidth gradually, such as 802.11a, xDSL, Bluetooth, GSM, and WCDMA.
Analog-to-digital converters based on the delta ΔΣ modulators have become popular in various applications. Due to the wide bandwidth requirement of modern communication and network, however, the low-order single-bit ΔΣ modulator cannot suit in wide bandwidth applications. Therefore, the high-order multi-bit ΔΣ modulator is necessary in wide bandwidth applications. With the improvement of the VLSI technique, all of these modules are expected to integrate for less chip area, low cost, and low power consumption. Therefore, the SOC (System on a Chip) and low power consumption are the most important concepts in the development for the modern communication and network systems.
In this thesis, we want to design wideband, lower power delta sigma modulator for WCDMA and GSM dual bandwidth and 802.11a applications. Furthermore, the circuit non-idealities effects also can be included in our architectures to predict the final performance of actual the ΔΣ modulators. According to these non-idealities models and analyses, we can obtain the optimum circuit specifications to implement our ΔΣ modulators. Therefore, the design cycle time can be reduced effectively and the circuits also can be implemented based on these optimum specifications.
In this thesis, a wideband, lower power ΔΣ modulator for W-CDMA and GSM dual bandwidth application is implemented in a standard 0.18-μm 1P6M CMOS technology. For the W-CDMA applications, the measurements indicate a dynamic range of 68dB and a SNDR of 61dB. For the GSM applications, the measurements indicate a dynamic range of 76dB and a SNDR of 70dB. The core area is 0.84mm2, and the power consumption is 28-mW at 1.8V. Another lower power ΔΣ modulator in applications of 802.11a is implemented in a standard 0.18-μm 1P6M CMOS technology, too. The simulation results show that the bandwidth is 10MHz；the sampling frequency is 160MHz；the dynamic range and the peak signal to noise ratio are 74dB and 70 dB respectively, and the total power dissipation is 38-mW at 1.8V.
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