DESIGN OF 5.2GHz CMOS DIFFERENTIAL LOW NOISE AMPLIFIER

碩士 === 大同大學 === 電機工程研究所 === 93 === This thesis describes the RF IC design concept, several important parameters and circuit and noise analysis of low noise amplifier first. Differential LNA has not only the ability of rejecting the common-mode noise, but also the nature ability of canceling the even...

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Bibliographic Details
Main Authors: Chih-Chang Jiang, 江志昌
Other Authors: Cheng-Ching Huang
Format: Others
Language:en_US
Published: 2005
Online Access:http://ndltd.ncl.edu.tw/handle/37118388186402276080
Description
Summary:碩士 === 大同大學 === 電機工程研究所 === 93 === This thesis describes the RF IC design concept, several important parameters and circuit and noise analysis of low noise amplifier first. Differential LNA has not only the ability of rejecting the common-mode noise, but also the nature ability of canceling the even-order distortions. In this thesis, we design a differential LNA that has better result representations, through using of inductive source degeneration, choosing of suitable device parameter and low impedance characteristic of the transistor source side to achieve input and output impedance matching. We employ TSMC CMOS 0.18μm process to design the LNA. With a supply voltage 1.8V, the simulation results for the differential LNA at 5.2GHz are as follows: input return loss is 28.763dB, output return loss is 14.999dB, gain is 12.884dB, noise figure is 2.369dB, P1dB is -14.002dBm, and the OIP3 is -3.56dBm. Power consumption is 15mW.