| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 94 === This thesis presents a low complexity high quality integer motion estimation IP design for MPEG /H.264 video coding applications. The proposed design is based on a low complexity algorithm which reduces over 90% complexity at the cost of less than 0.2dB PSNR drop as compared to full search block matching algorithms. Moreover, we have also exploited pixel truncation and special memory access operations to reduce the hardware cost and memory bandwidth. According to TSMC 0.18um CMOS technology, the proposed design costs 61.2K gates, Cur/Ref. pixel buffer with 4Kbits and 26.5Kbits/87.9Kbits local memory for search range [-16, 16) and [-40, 40) respectively. The maximum operating frequency of the proposed design is 115MHz and it can achieve real-time motion estimation on QCIF, CIF, SDTV (720x480) and HDTV (1280x720) video operated at 10, 20, 40, and 108 MHz, respectively.
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