Power-aware Register Renaming for Multi-banked Register Files
碩士 === 長庚大學 === 資訊工程研究所 === 95 === The multi-banked register file (MBRF) is one of the effective approaches to resolve the complexity of the monolithic register files. In order to apply the multi-banked register file to a high-end embedded processor, we design the dynamic voltage scaling (DVS) appro...
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ndltd-TW-094CGU003920122016-05-25T04:14:05Z http://ndltd.ncl.edu.tw/handle/08672993125346155855 Power-aware Register Renaming for Multi-banked Register Files 多重暫存器檔案之低電耗暫存器重命名法 Chang-Yi Lee 李昌益 碩士 長庚大學 資訊工程研究所 95 The multi-banked register file (MBRF) is one of the effective approaches to resolve the complexity of the monolithic register files. In order to apply the multi-banked register file to a high-end embedded processor, we design the dynamic voltage scaling (DVS) approach for MBRF to satisfy the energy constraints. However, we found that distributed bank-access behavior prevents voltage scaling from identifying when a bank is active or not. To resolve this problem, in this paper, we analyze the access behavior of short-lived values, and change their storage in banks. The goal is to increase the opportunities of power saving for register banks storing non-short-live values. We then turn these register banks into the lower mode by our proposed DVS circuit. For a four-banked register file architecture, simulation results show that, on average, our approach reduces about 84% energy consumption while performance loss can be limited by less than 10%, compared with a register file without DVS. Wann-Yun Shieh 謝萬雲 2007 學位論文 ; thesis 41 en_US |
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碩士 === 長庚大學 === 資訊工程研究所 === 95 === The multi-banked register file (MBRF) is one of the effective approaches to resolve the complexity of the monolithic register files. In order to apply the multi-banked register file to a high-end embedded processor, we design the dynamic voltage scaling (DVS) approach for MBRF to satisfy the energy constraints. However, we found that distributed bank-access behavior prevents voltage scaling from identifying when a bank is active or not. To resolve this problem, in this paper, we analyze the access behavior of short-lived values, and change their storage in banks. The goal is to increase the opportunities of power saving for register banks storing non-short-live values. We then turn these register banks into the lower mode by our proposed DVS circuit. For a four-banked register file architecture, simulation results show that, on average, our approach reduces about 84% energy consumption while performance loss can be limited by less than 10%, compared with a register file without DVS.
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Wann-Yun Shieh |
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Wann-Yun Shieh Chang-Yi Lee 李昌益 |
author |
Chang-Yi Lee 李昌益 |
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Chang-Yi Lee 李昌益 Power-aware Register Renaming for Multi-banked Register Files |
author_sort |
Chang-Yi Lee |
title |
Power-aware Register Renaming for Multi-banked Register Files |
title_short |
Power-aware Register Renaming for Multi-banked Register Files |
title_full |
Power-aware Register Renaming for Multi-banked Register Files |
title_fullStr |
Power-aware Register Renaming for Multi-banked Register Files |
title_full_unstemmed |
Power-aware Register Renaming for Multi-banked Register Files |
title_sort |
power-aware register renaming for multi-banked register files |
publishDate |
2007 |
url |
http://ndltd.ncl.edu.tw/handle/08672993125346155855 |
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