A Low Power Driven Voltage Scaling Algorithm Using Dual Supply Voltage at Placement Stage

• Main Authors: Hung-Hsie Lee, 李鴻禧
• Other Authors: Mely Chen Chi
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/72941162832651866576

碩士 === 中原大學 === 資訊工程研究所 === 94 === With the improvement in the process technology, IC industry enters the deep sup-micron era, the number of cell on ICs increases dramatically. Power consumption has become one of the most important issues in a design theme. The method of using lower supply voltage to reduce power dissipation is a recent trend, but this technique has not been combined with the development in the physical design. In this paper we research the relation between placement and voltage scaling technique. There are three major phases in this algorithm. In the first phase, we develop a timing driven placer and a basic force directed placer. We place standard cells to its force-balanced position by using forced directed algorithm. And then according to the relative position of cells, we place cells until each cell is not overlapped to another. The second phase is voltage scaling phase. In this phase, we use the method “partition based voltage scaling” [2]. We add a new cost which is the distance between high voltage supply and gate into the gain of this method. The third phase is to create voltage rows and fix timing violation. We create high and low voltage rows according to the position of high and voltage cells, and then we move cells to the corresponding rows. After moving cells, if timing is incorrect, we fix the timing by gate sizing to guarantee that the timing is correct. In comparison with the power consumption of the circuit after placement, on average, our algorithm reduces the power consumption of the basic force directed placement by 45.1%, the power consumption of the timing placement by 45.6%, and the power consumption of commercial tool Placement(Cadence/SOC Encounter) by 36.7%.