Physical Design System Construction and Algorithms Development

• Main Authors: Jun-Cheng Chi, 紀俊呈
• Other Authors: Mely Chen Chi
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/83500443957858911179

博士 === 中原大學 === 電子工程研究所 === 94 === Abstract In this thesis, we develop a physical design system. First, an architecture of the physical design system is proposed. This architecture consists of a central database, a LEF/DEF translator, a set of access utilities, a set of optimization processes, and a graphic user interface. The architecture is easy to be extended and maintained. Based on the architecture, an integrated timing-driven partitioning, floorplanning, and placement system has been constructed. In both floorplanning and placement stages, two novel timing-design methodologies are proposed to optimize the timing of the circuit. During the system flow, we use the same critical path information and the same models for delay estimation to increase the consistency of the cost functions in different stages. The timing-driven system is also integrated with a commercial CAD design flow. The system is continuously enhanced with the progress of the VLSI design. In this thesis, we also study the problems which are accompanied with the advancing of the VLSI process. We present the algorithms in the areas of the floorplan, placement, and low power design methodologies. An effective hard/soft modules floorplanning algorithm is proposed. It uses simulated annealing framework based on the sequence pair representation. We proposed a method which finds four candidates of module shape to be chosen in a simulated annealing process for each module. These candidates provide a better choice toward local optimal packing. The proposed algorithm may be extended to handle the connectivity and different placement constraints. Experimental results show that the approach is very effective. At placement stage, we proposed an IR drop-driven standard cell placement algorithm which simultaneously minimizes the maximum IR drop of a design and considers the critical path delay. The proposed algorithm can reduce the maximum value of IR drop among all rows at the placement stage. Experimental results show that the proposed algorithm may produce a placement with lower maximum IR drop value compared to the Cadence/QPlace. The placement with a lower maximum IR drop is more reliable and needs less power/ground straps or a coarser power grid in the design. Thus, more routing resources can be used for routing signal nets. With the advancement of technology, VLSI designs will become more complex with higher frequencies and lower supply voltages. It will cause more serious IR drop and timing closure problems. Finally, we also study the multiple voltages scaling problem for low power designs. A two-phase voltage scaling algorithm for VLSI circuits is proposed. The proposed algorithm utilizes the slack of each gate to scale down the voltages of the gates. It combines a greedy approach and an iterative optimization method to scale the supply voltage of gates effectively. Our study also shows the lower bound value of the voltage domains is the main factor in determining power savings. If more voltage domains are used, more voltage islands will be needed and designers will be burdened with the chore of accommodating the extra voltage islands in their designs. Thus, using dual voltage domains is a good choice both for saving power and facilitating the design effort. By applying lower supply voltages on non-timing critical gates, we can greatly reduce the total power consumption.