System Level Verification and Simulation Platform for the IEEE 802.11e Ad-Hoc QoS Silicon Intellectual Property with Cross-Layer Control

• Main Authors: YangHsin-Long, 楊欣龍
• Other Authors: Chao-Lieh Chen
• Format: Others
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/71455108133447752010

碩士 === 崑山科技大學 === 電子工程研究所 === 94 === We study QoS control and experimental performance analysis for multimedia streaming over wireless ad-hoc networks. A Media Access Control (MAC) centric cross-layer control for the QoS purpose is proposed. Considering Silicon Intellectual Property (SIP) implementation of the QoS controller, we adopt the network simulator, NS-2, as test bench and integrate it with the EDA tools to constitute a system level simulation and verification platform. Traditional OSI model has independent protocol layers. Signaling between two layers requires intervention of operating system. Different layers cannot signal to each other adlib. This inflexibility limits the multimedia streaming over wireless networks due to there are too many uncertain dynamics such that traditional OSI protocol structure cannot handle them cognitively. Therefore, we propose the Hierarchical Cross-Layer Control (HCLC) for QoS management. We regards the wireless LAN as the plant and adopts fuzzy feedback control to model and analyze the IEEE 802.11e enhanced distributed channel access (EDCA). After optimization, SIP implementation of the MAC layer controller is proposed for future integration in network communication SoCs. The SIP simulation and verification are performed without porting of system software and drivers. Traditional system level verification requires other SIPs’ models including the CPU model such as the easy arm design kit provided by the Chip Implementation Center. In the CPU model, engineers need to develop system software to control all signaling and data flows. To ease the verification, we integrate the NS-2 with EDA tools to replace the host CPU such that porting of operating system, protocol stacks, and drivers are economized and the SIP development cycle is shorten. The network scenario and events are feed into hardware descriptions and Field Programmable Gate Array (FPGA) as test benches. In this way, SIP designers are able to perform not only signal level simulation but also more persuasive system level verifications with more realistic network scenarios. This verification platform saves much costs and time in development of communication networking SoCs. We perform extensive simulations for the multimedia streaming. We use MPEG4 video streaming examples. With background and still enough bandwidth capacity, HCLC preserves bandwidth for other traffics. When the environment becomes crowded with other traffics and remaining bandwidth is critical, the HCLC preserves fairness and video qualities of multimedia streams are assured. The experiments show that even when the network bursts, both software and hardware implementation of the HCLC control provides real-time allocation of bandwidths, reduces packet delay, smoothes packet jitter, and preserve fairness at the same time. We not only accomplish cross-layer QoS HCLC control algorithm but also the HCLC SIP system level simulation and verification platform.