Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI

碩士 === 立德管理學院 === 應用資訊研究所 === 94 === Based on the conventional simulated annealing algorithm, the construction of high efficient orthogonal simulated annealing algorithm is proposed in this thesis that makes use of various perturbation mechanisms and systematizes the current solutions into a group o...

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Main Authors: Tien-Te Wang, 王天德
Other Authors: Jenn-Long Liu
Format: Others
Language:zh-TW
Published: 2006
Online Access:http://ndltd.ncl.edu.tw/handle/80820721379433412508
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spelling ndltd-TW-094LU0055850112016-06-01T04:14:20Z http://ndltd.ncl.edu.tw/handle/80820721379433412508 Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI 高效率直交模擬退火法建構及其於VLSI平面規劃之應用 Tien-Te Wang 王天德 碩士 立德管理學院 應用資訊研究所 94 Based on the conventional simulated annealing algorithm, the construction of high efficient orthogonal simulated annealing algorithm is proposed in this thesis that makes use of various perturbation mechanisms and systematizes the current solutions into a group of possible solutions with a few perturbation operations required. By using the factorial analysis in the orthogonal experimental design, an Intelligent generation mechanisms for new solution contained with a group of perturbation operations will be deduced from the former operation results. Eventually an accurate and best perturbation group in vicinity will quickly come into being and we can get the optimal solution. In order to disclose the differences between the orthogonal and the conventional simulated annealing algorithm, This thesis first of all, has done severval experiments with operating ten factorial formulae with varied difficulties. It shown that the results from the former algorithm are better than from the latter one. Secondly, sequence pair representation is introduced into the VLSI floorplanning to reflect the placement of each construction group. Finally, five standard testing modules such as MCNC (Apte, Xerox, Hp, Ami33, Ami49)are evaluated. These results shown that the measures put forward in this thesis and other research products in related works will perfect the current measures effectively on the solution of grand floorplanning. Jenn-Long Liu 劉振隆 2006 學位論文 ; thesis 58 zh-TW
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description 碩士 === 立德管理學院 === 應用資訊研究所 === 94 === Based on the conventional simulated annealing algorithm, the construction of high efficient orthogonal simulated annealing algorithm is proposed in this thesis that makes use of various perturbation mechanisms and systematizes the current solutions into a group of possible solutions with a few perturbation operations required. By using the factorial analysis in the orthogonal experimental design, an Intelligent generation mechanisms for new solution contained with a group of perturbation operations will be deduced from the former operation results. Eventually an accurate and best perturbation group in vicinity will quickly come into being and we can get the optimal solution. In order to disclose the differences between the orthogonal and the conventional simulated annealing algorithm, This thesis first of all, has done severval experiments with operating ten factorial formulae with varied difficulties. It shown that the results from the former algorithm are better than from the latter one. Secondly, sequence pair representation is introduced into the VLSI floorplanning to reflect the placement of each construction group. Finally, five standard testing modules such as MCNC (Apte, Xerox, Hp, Ami33, Ami49)are evaluated. These results shown that the measures put forward in this thesis and other research products in related works will perfect the current measures effectively on the solution of grand floorplanning.
author2 Jenn-Long Liu
author_facet Jenn-Long Liu
Tien-Te Wang
王天德
author Tien-Te Wang
王天德
spellingShingle Tien-Te Wang
王天德
Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI
author_sort Tien-Te Wang
title Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI
title_short Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI
title_full Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI
title_fullStr Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI
title_full_unstemmed Construction of High Efficient Orthogonal Simulated Annealing and Its Application to the Floorplanning of VLSI
title_sort construction of high efficient orthogonal simulated annealing and its application to the floorplanning of vlsi
publishDate 2006
url http://ndltd.ncl.edu.tw/handle/80820721379433412508
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