An Alternative LRU Hardware Implementation Based On Multiplexer

• Main Authors: Chia-Chou Tsai, 蔡佳洲
• Other Authors: 張延任
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/ux499p

碩士 === 國立中興大學 === 資訊科學系所 === 94 === Abstract In an embedded processor, in order to lower power consumption, it needs to reduce cache misses that cause the data exchange between the cache memory and the DRAM memory. Since DRAM is off-chip, the power consumption of accessing the off-chip DRAM is about 200 times larger than the power consumption of accessing the on-chip cache. In order to reducing cache misses, we utilize the LRU replacement policy to decrease the frequency of the data exchange between the cache memory and the DRAM memory. Comparing with the Random and FIFO replacement policy, LRU replacement policy has lower miss rate. But implementing LRU replacement policy is more difficult than Random and FIFO, it needs extra memory devices to store the information of the referenced order of the each block and control circuit to update the information in the memory device. Undoubtedly, these extra costs can affect the whole performance of the embedded processor. In this thesis, we propose a method which bases on multiplexer to implement LRU hardware. This method not only improves performance of updating referenced order of each block, but also effectively reduces power and energy consumption. In 32-way set-associative cache, we propose the method to compare with the LRU Array, and then we can save 64.6% transistor counts, 45% power consumption, 46% energy consumption, and improve 1.17% performance. Comparing with the comparator-based LRU circuit, our method also saves 6.7% transistor counts, 30% power consumption, 39% energy consumption, and improves 7.74% performance. Finally, our method compares with the Random replacement policy, and then we can save 8.3% total energy consumption.