VLSI Design of A Parallel CRC-32 with Single Error Correction

• Main Authors: Min-Dong Li, 李民棟
• Other Authors: 范志鵬
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/32323052237244885214

碩士 === 國立中興大學 === 電機工程學系所 === 94 === How do we want to decide corrects in data at receivers for communications and networks? In general, the cyclic redundancy check (CRC) is popular used for checksum computation. Cyclic redundancy check (CRC) is a powerful class of code, which suits especially for the detection of burst errors in data storage, communication applications, testing of integrated circuits and the detection of logic faults. CRC acts powerful class of codes for applications, but when the process speed is up to 10 Gbps, the implementations of header error corrections in hardwares can be a bottleneck. At current networks, the speed of communication transmissions is more and more fast. If CRC processes can not speed up to 10 Gbps, it will not achieve the real-time high-speed transmissions and communications. Thus, the high-speed CRC is required to solve the error detection problem in high-speed networks. In this thesis, we improve hardware architectures in [1] [2] and combine two architectures to implement an effective CRC-32 hardware on FPGA device. The proposed CRC-32 module not only detects CRC error and corrects one bit error but also determines where the one-bit error is in the received information or in the checksum. So we can find out and correct one bit error by additional checksum computations. We improve parallel CRC circuits in [1], which only can deal with input data to be divisible by the polynomial. The proposed CRC-32 can deal with input data, which can not be divisible by the polynomial. We expand one-bit correct ability from 16 bits to 32 bits for increasing error correct performances.