FPGA Implementations of High Speed Sequential and Fully Pipelining AES Modules

• Main Authors: Jun-Kui Huang, 黃俊魁
• Other Authors: 范志鵬
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/04835919834779717673

碩士 === 國立中興大學 === 電機工程學系所 === 94 === Due to the universal applications of wireless networks, the security of data becomes more and more important. Nation Institute of standards and Technology (NIST) was announced an advanced encryption standard (AES) to become the new encryption and decryption standard, which has been used in CCMP communication protocol for the IEEE 802.11i standard. The IEEE 802.11i standard must use many AES modules in CCMP communication protocol, and apply to more and more data transmission circumstances. In order to increase throughputs effectively, increasing speed for AES module is very important. In this thesis, the major consideration is the high speed application. We implement the AES encryption and decryption chip with the Xilinx Field programmable Gate Arrays (FPGA) chips. We propose a novel hardware architecture for the implementation of SubBytes (S-box) module. The SubBytes (S-box) module can achieve the high speed process in AES module. Then we design three different pipelining architectures that can increase throughputs in AES module. In sequential architecture, the throughput rate can reach to 0.876 Gbps. In multi-round pipelining architecture, the throughput rate can reach to 1.48 Gbps. In full pipelining architecture, the throughput rate can reach to 32 Gbps.