| Summary: | 碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 94 === As the process technology growing, the total gate count in a single chip has farther beyond our imagination. Comes the digital age, there are more and more complex IC design requirements. In this situation, traditional IC design flow can not follow the highly growing and demanding requirements. For design breakthrough, we must make improvements from our design methodology, to increase the reliability, and speed up design and verification time, to cut down time to market.
In this thesis, a novel progressive hardware design/verification flow is proposed. This flow covers from the beginning of algorithm/system modeling/partitioning with C language model to the end of design verification on FPGA. Design verification is the main issue of this flow. The result produced in each design phase of the proposed design flow can be used in the verification of the next design phase. In addition, generating test vectors and comparing the results on both simulation model and real circuit in FPGA are also achieved during this flow. At the end of this thesis, we take currently popular video encoding system – H.264 as a design example, to explain this novel design flow. In our experiences the proposed design flow greatly reduces the time spent on verification and debugging which occupy most of the design time of a product.
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