| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === With the rapid development of information technology, an analog-to-digital converter is found critically needed in novel electronic products and high-speed communication circuits. Therefore, this paper has proposed a 10-bit two-step analog-to-digital converter embedded with the improved capacitor interpolation circuit as well as a novel amplifier, where the settling time is seen relatively short when compared to other methods. This completed converter can process 250 million samples per second. In the design, the low power consumption, voltage offset, and noise interference were all included into the considerations. To validate the effectiveness of this method, with the aid of TSMC 0.18 1P6M CMOS process, the circuit simulation software HSPIC was utilized, by which the simulation results obtained helped support the feasibility of the proposed design.
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