A 0.7-V 10-bit Ultra-low Power Cyclic A/D Converter with Digital Foreground Calibration
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === This paper describes a low supply voltage and ultra-low power integrated analog-to-digital converter (ADC) for implantable bio-medical sensor applications. Through biasing the opamps and comparators in the weak-inversion region and adopting switched-opamp tech...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06945966350584742713 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === This paper describes a low supply voltage and ultra-low power integrated analog-to-digital converter (ADC) for implantable bio-medical sensor applications. Through biasing the opamps and comparators in the weak-inversion region and adopting switched-opamp technique into the ADC architecture allows for the circuit operation with low supply voltage and ultra-low power consumption. A 0.7-V 10-bit 1 ksample/s ultra-low power cyclic analog-to-digital converter (ADC) is proposed, which is itself calibrated in the foreground and implemented with 0.13μm TSMC 1P8M CMOS technology. The calibration overcomes the circuit non-idealities caused by capacitor mismatch and finite operational amplifier (opamp) gain in the cyclic ADC. With the digital foreground calibration, the peak signal-to-noise ratio is 58.86 dB with a low gain (53 dB) but linear opamp. The total power dissipation is 2 μW not including the calibration circuit.
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