Research of CMOS 4/8-GHz Dual-Band Frequency Synthesizer and RFICs For DS-UWB Receiver

• Main Authors: Jhan-Yu Lin, 林展裕
• Other Authors: Chun-Lin Lu
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/09889080204534912405

碩士 === 國立成功大學 === 電腦與通信工程研究所 === 94 === 　This thesis presents the research on CMOS 3-5-GHz broadband LNA, 4/8-GHz dual-band VCO, 4/8-GHz dual-band frequency synthesizer, and integrated circuit RFICs for DS-UWB applications. The RFICs are fabricated in a TSMC standard 0.18-μm CMOS precess. The circuit measurement is performed using a FR-4 PCB test fixture. The 3-5-GHz broadband LNA exhibits a gain of 12.1-18.6 dB, input return loss and output return loss are higher than 10 dB, input P1dB is -17.2- -26.7 dBm, IIP3 is -11.2- -17.9 dBm, and noise figure is less than 5.48 dB. The 4/8-GHz dual-band VCO exhibits an output frequency from 4154 to 4358 MHz in low band, and from 8128 to 8556 MHz in high band. The dual-band VCO with divided-by-4 chip and Motorola MC12210 PLL chip form a frequency synthesizer. While output frequency locks at 4.3 GHz, the phase noise is -84.6 dBc/Hz@100-kHz offset, and locks at 8.6 GHz, the phase noise is -81.7 dBc/Hz@100-kHz offset. The dual-band frequency synthesizer includes dual-band VCO, phase/frequcney detector, charge pump and frequency divider. After modify the value of capacitor, the dual-band VCO can be locked in desired frequency. The frequency synthesizer and broadband mixer is integrated. In frequency synthesizer, the VCO output frequency is from 4192 to 4367 MHz. And when output frequency is locked in 4.3 GHz, the phase noise is -88.7 dBc/Hz@100-kHz offset. The broadband mixer exhibits a gain of -0.9- -6.1 dB, input P1dB is -5.1- -8.8 dBm, IIP3 is -2.6-2.2 dBm, and noise figure is less than 16.12 dB. The 3-5-GHz front-end includes LNA, active balun, and mixer, it exhibits a gain of 9.1-14.4 dB, input P1dB is -25.2 - -16 dBm, IIP3 is -16.7- -6.75 dBm, and noise figure is less than 11.15 dB. Detail measurement and each chip performance problem presented and discussed.