| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 94 === Clock and data recovery circuit is an important component in digital communication systems. The applications include many point-to-point digital transmission systems, such as Asynchronous Transfer Mode (ATM), Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), Fiber Distributed Data Interface (FDDI), Ethernet, Wavelength Division Multiplexing (WDM), Dense Wavelength Division Multiplexing (DWDM) and interface of universal serial bus (USB) between personal computer and external device. In recent years, the high-speed serial link has also encroached on the board level as a standard interface of host computer to reduce the transmission line and power consumption, such as serial-ATA and PCI-express.
In the thesis, a low-voltage clock and data recovery circuit with PLL-based topology in 0.35μm process. Phase and frequency detector adopts differential scheme for low-voltage operation. In addition, a modified voltage-controlled oscillator is proposed to improve linearity of frequency-voltage characteristic curve and reduce gain and noise sensitivity. The circuits are implemented in TSMC 0.35μm 2P4M and operating frequency is 1 GHz. The measured tuning range of improved VCO is from 900 MHz to 1160 MHz at 1 GHz, peak-to-peak and root-mean-square jitter are 11.64ps and 1.36ps, respectively. The measured phase noise is -110.4 dBc/Hz at 1-MHz offset from a 1.005-GHz center frequency. Power consumption is 32.5 mW. The measured peak-to-peak and root-mean-square jitter of the clock and data recovery under 1.8 V are 348.27 ps and 58.05 ps, respectively. Power consumption is 37.7 mW. The chip area included test circuits and pads is 1520×914 μm2.
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