Chip Design of Mel Frequency Cepstral Coefficient for Speech Recognition

• Main Authors: Ying Lei, 雷穎
• Other Authors: Gin-Der Wu
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/69494964042006361607

碩士 === 國立暨南國際大學 === 電機工程學系 === 94 === This paper proposed the chip design of speech recognition for multimedia system. It is composed by three cores: a low-power high performance fast fourier transform (FFT) processor, a Mel-scale frequency cepstral coefficient (MFCC) circuit, and a dual-ALU digital signal process (DSP) processor with dynamic time warping speech recognition algorithm. The DSP processor had been implemented by previous researcher. In this paper, we mainly proposed the FFT processor and MFCC chip. In the FFT processor, we proposed a novel register array based pipelined radix-2 structure to reduce power consumption and computation cycles. In the MFCC circuit, we adopt one pair of accumulation procedure to reduce the computation of Mel frequency bank. In addition, we also minimize the look-up table size for logarithm operations, and we use gating clock issue to reduce power consumption. The two chips are synthesized by TSMC 0.18um cell library. The die size of the FFT/IFFT processor is approximately 4.73 . And the die size of the MFCC chip is approximately 1.71 . The two chips both work at 100 MHz.