| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 94 === Hand-held devices such as personal digital assistants (PDAs) and cellular phones are getting more and more popular in recent years. Energy consumption is a critical issue because these devices are battery powered. Dynamic voltage scaling (DVS) is a low-power design technique that adjusts the CPU frequency and voltage levels dynamically based on CPU workloads. The performance of a DVS algorithm largely depends on how to estimate slack time accurately. In this thesis, we propose a deferred-workload-based inter-task DVS algorithm (dwDVS), which has two features. The first is that we reserve a time interval for each task to execute and its workload can be completed in this time interval even in the worst-case condition, which means that the actual workload (execution time) of each task is equal to its worst-case execution time. In this way, we can estimate the slack time from lower priority tasks more aggressively. The second is that we defer these reserved time intervals, which means that a reserved time interval will be shifted to the deadline of its corresponding task as close as possible. In this way, the operating frequency can be reduced even without slack time. Simulation results show that the proposed dwDVS reduces the energy consumption by 40-70%, 10-20%, and 3-10% compared with the static voltage scaling (Static) [1], laEDF [1], and DRA [2] algorithms, respectively, and approaches theoretical low bound (Bound) by an margin of at most 12%.
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