Efficient Datapath Design for Clustered & Pipelined VLIW DSP Processors
碩士 === 國立交通大學 === 電子工程系所 === 94 === Most DSP applications feature a high degree of data-level and instruction-level parallelism, which enables efficient datapath design with clustering and deep pipelining. However, the ad-hoc data forwarding and inter-cluster communications in most processors signif...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24419684455805579987 |