| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 94 === Among all architectures of analog-to-digital converter (ADC), the pipeline architecture was widely used in applications with high speed and high resolution, due to its small size and low power consumption. If we want to achieve higher speed and more accuracy, there are some errors to overcome. Such as capacitor mismatch, operational amplifier gain error, bandwidth limitation, comparator threshold offset and so on. In this thesis, we present a new operational amplifier with positive feedback technique to reduce its gain error and input parasitic capacitance, it is well suited to implement ADC with high performance.
In this thesis, a fully differential 3.3V, 10-bit, 40M sample/sec pipelined ADC with a 1.5-bit stage digital error correction has been designed with TSMC 0.35-μm double-poly four-metal CMOS process. The components in this ADC include residue amplifier, comparator, flip-flop, adder, clock generator and front-end sample-and-hold(S/H). The input range is -1V~+1V.
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