The Study of FFT Processors for OFDM Systems

• Main Authors: Yu-Wei Lin, 林昱偉
• Other Authors: Chen-Yi Lee
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/89995271247315306463

博士 === 國立交通大學 === 電子工程系所 === 94 === Orthogonal Frequency Division Multiplexing (OFDM) technique provides an efficient way to overcome a multipath-fading environment. Because lots of advanced digital signal processing is used in this system, the computational complexity of OFDM is high. The Fast Fourier Transform (FFT) is one of the highest computational components. The specification of FFT which varies with different OFDM systems must be considered when we design the FFT processor. In this dissertation, we focus on three OFDM systems such as digital video broadcasting – territorial (DVB-T), Ultra-wideband (UWB), and IEEE 802.11n and propose three novel FFT architectures for these applications. In a DVB-T system, an 8192-point FFT processor, in which a 3-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer are proposed. About 64 K bit memory space can be saved in the 8 K-point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 um single-poly six-metal (1P6M) CMOS process with core area of 4.84 mm2. Power dissipation is about 25.2 mW at 20 MHz In a UWB system, the proposed pipelined FFT architecture called Mixed-Radix Multi-Path Delay Feedback (MRMDF) can provide higher throughput rate by using the multi-data-path scheme. Furthermore, the hardware costs of memory and complex multiplier in MRMDF are only 38.9% and 44.8 % of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for UWB system has been designed and fabricated using 0.18 um 1P6M CMOS process with core area of 1.76 x 1.76 mm2, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 G sample/s while it consumes 175 mW. Power dissipation is 77.6 mW, when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 M sample/s. In a IEEE 802.11n system, the proposed processor based on multi-data-path scheme not only supports the operation of FFT/IFFT in 128 points and 64 points but also can provide the different throughput rates for 1~4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with the traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13um single-poly and eight-metal CMOS process. The core area is 660 x 2142 um2, including an FFT/IFFT processor and a test module. At the operation clock rate of 40 M Hz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 us.