| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 94 === In this thesis, we studied the process technologies and device characteristics of novel SOI tri-gate FETs (TGFETs) and low-temperature poly-Si TFTs with NiSi films. Including thermal stability of NiSi films on different substrates, the control of lateral silicidation length by a two-step annealing method, applications of ITS technique on the S/D and gate electrodes of TGFETs were studied. Next, the impacts of channel width, side-gate depth, and back-gate bias on the device reliability were studied. Finally, to apply on the system-on-panel (SOP), poly-Si TFTs with modified Schottky-barrier (MSB) S/D junction and HfO2 gate dielectric layer were researched, respectively.
First of all, we demonstrated that the NiSi films on the SiO2 substrate, without the excess Si atoms, have superior thermal stability. At the same time, using a special four-terminal sheet resistance test structure, the two-step annealing method was also found to well control the lateral silicidation length.
Next, a novel 25nm modified-Schottky-barrier (MSB) SOI TGFET with NiSi S/D electrodes was fabricated by the low temperature two-step (300oC+600oC) NiSi silicidation and ITS technique. In this MSB TGFETs, low S/D external resistance, well-controlled NiSi profile, low temperature activation process, low S/D leakage current, and the high driving current owing to the MSB junction fabricated by ITS technique were also demonstrated.
Besides, the reliability issues of TGFETs were also detail investigated. As the channel width reduces, not only the side-gate bias could effectively reduce the electric field in the channel and disperse the direction of hot-carriers, but the flatness of narrow silicide front-end was also another plausible reason that the device reliability could be enhanced. Moreover, deeper side-gate depth (DEXT) with narrower channel width structure was also demonstrated to shield the electric field from back-bias and then relaxed the influence of defects in the interface and bulk region of buried oxide.
To solve the device performance degradation caused by poly-Si gate depletion effect while simplify the fabrication process, we also suggested the novel FUSI gate structure on the MSB FD-SOI devices by the same ITS technique. Using the ITS technique, the S/D and gate electrode could be fabricated easily at the same time. During this process, the poly-gate depletion could be suppressed; the work function could be suitable tuned. More important, this gate electrode engineering could be compatible with the fabrication process of MSB S/D junction. To conclude, these novel devices could be applied on high-speed device and radio-frequency circuits.
In this thesis, we also illustrated the ITS technique on the fabrication of S/D electrodes of low-temperature poly-Si TFTs. For fabrication process, because of the low thermal budget, the throughput could be improved effectively. For electrical characteristics, smaller S/D parasitic resistance, larger Ion/Ioff current ratio, smaller subthreshold swing, smaller operation voltage, higher effective field mobility, and stable reliability were approached. Moreover, because of the superior short channel characteristics, the novel FSD TFTs were suggested to scale down to the nano-scale regime.
Finally, a novel poly-Si TFT using a low-temperature and thin high-k (HfO2) film as gate dielectric was fabricated. In this device, the effective oxide thickness (EOT) could be scaled down to 7.3nm, and low gate leakage current could be maintained. The electrical characteristics including Ion/Ioff (~107), subthreshold swing (~0.28V/Dec), and threshold voltage (0.3V) were also approached. Combining the HfO2 gate dielectric with thin EOT and the ultra-narrow channel width structure, the novel HfO2 TFT was also verified to the future system-on-panel (SOP) applications.
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