Design of a 1.8 -V CMOS LNA applied for Ultra-Wideband 3.1 to 10.6GHZ Wireless Receivers

• Main Author: 邱子倫
• Other Authors: 荊鳳德
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/16412336720670592371

碩士 === 國立交通大學 === 電子工程系所 === 94 === A low noise amplifier is applied for ultra-wideband. This research is fabricated in 0.18-μm CMOS process. The three-order band-pass Chebyshev filter can reach the broadband input impedance matching. Owing to the low power consideration, plus the additional gate capacitor . The cacoded structure gain stage provides the gain of the amplifier. The capacitor reduces the gain degradation caused by at high frequency. The inductive shunt peaking maintain the gain flatness. Output buffer is used for output broadband matching. The low noise amplifier introduces the shunt peaking to achieve the flat gain purpose. The total power dissipation of the chip is about 18 mW at power supply 1.8 volt. The chip size included pad is 0.992 mm2. The measurement result of this study expect that the forward gain S21 is 6 to 9.7dB at 3.1-10.6GHz, the reverse isolation S12 is under -20dB, the average S11 is under -7 dB, the average S22 is under -10dB, the noise figure minimum is 6dB, and IIP3 is 6dBm.