Back-Gate Bias Control on Subthreshold Circuit Mismatch and its Physical Model

• Main Authors: Kuei-Hung Tseng, 曾貴鴻
• Other Authors: Ming-Jer Chen
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/44648170610127234064

碩士 === 國立交通大學 === 電子工程系所 === 94 === 　　This thesis investigates the back-gate bias control on subthreshold circuit mismatch as well as its physical model. We have measured the MOSFETS operating in subthreshold (or called weak inversion) to above-threshold regions with different gate widths and lengths. These MOSFETS were characterized with back-gate reverse and forward biases. The first observation is that the devices operating in subthreshold region exhibit larger mismatch than those in above-threshold region. This is due to the exponential dependence of current on gate and bulk voltages as well as process variations. In the case of back-gate reverse bias, we have found that current mismatch increases as the magnitude of back-gate reverse bias increases. This phenomenon is more pronounced in subthreshold region than in above-threshold region. On the other hand, with the supply of back-gate forward bias, the current mismatch deceases with increasing the back-gate bias in all operation regions. The improvement in match is due to the gated lateral bipolar action in low level injection. With the data measured from devices with different sizes, we have found that small size devices not only exhibit larger mismatch, but also are more sensitive to the back-gate bias. Two suggestions are drawn from the experiment data: (i) subthreshold circuits should be carefully designed to suppress the mismatch; and (ii) the gated lateral bipolar action can be utilized to improve the matching property of MOSFET’s. 　　Besides the experiment, we have also derived a new simple analytical statistical model that has successfully reproduced the mismatch data in weak inversion for different back-gate biases and different device dimensions. With this model, the current mismatch can be expressed as a function of the variations in process parameters, namely, flat-band voltage and body effect coefficient. The extracted variations are shown to follow the inverse square root of the device area. Some examples have been given to demonstrate that the model is capable of serving as the quantitative design tool for the optimal design between the mismatch and device size with the back-gate forward bias as a parameter.