VLSI Crosstalk Fault Testing with Oscillation Signals
博士 === 國立交通大學 === 電子工程系所 === 94 === This dissertation studies several topics on testing and built-in self-testing of crosstalk faults of digital circuits with innovative methods which are related with oscillation signals. First, a test scheme for the induced-glitch type of the crosstalk fault by app...
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ndltd-TW-094NCTU54281312016-05-27T04:18:37Z http://ndltd.ncl.edu.tw/handle/12782483001913698645 VLSI Crosstalk Fault Testing with Oscillation Signals 以振盪信號測試超大型積體電路之串音障礙 Ming-Shae Wu 吳明學 博士 國立交通大學 電子工程系所 94 This dissertation studies several topics on testing and built-in self-testing of crosstalk faults of digital circuits with innovative methods which are related with oscillation signals. First, a test scheme for the induced-glitch type of the crosstalk fault by applying an oscillation signal on an aggressor line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines of the circuit under test (CUT). A set of symbols and associated algebra are defined to compute the propagation and detection of signals. It is simple and eliminates the complicated timing issue during test generation for the crosstalk fault in the conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show that the described test generation procedure is effective in generating test patterns for this scheme. Next, a BIST scheme based on a squarewave test signal to test also the induced-glitch type of the crosstalk fault of embedded circuits of SoC in the boundary scan environment for deep sub-micron VLSI is proposed. The scheme applies squarewave test signals in conjunction with pseudo random patterns to induce glitches which are caused by crosstalk faults and tests them. Modifications on boundary scan cells with simple added detection circuits to facilitate this test scheme are presented. Experimental results show that the average fault coverage obtained by applying the scheme to large size benchmark circuits can easily reach 90%. Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a pulse of specified width, CWP, to the victim line and detects the propagation of the CWP at the output of the victim line to detect the existence of crosstalk faults. Experimental results show that the detection quality is high when no time skew at test signals and no process variation on interconnects occurs. The scheme is simple and is considered effective in detecting crosstalk faults. Chung Len Lee 李崇仁 2006 學位論文 ; thesis 74 en_US |
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博士 === 國立交通大學 === 電子工程系所 === 94 === This dissertation studies several topics on testing and built-in self-testing of crosstalk faults of digital circuits with innovative methods which are related with oscillation signals. First, a test scheme for the induced-glitch type of the crosstalk fault by applying an oscillation signal on an aggressor line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines of the circuit under test (CUT). A set of symbols and associated algebra are defined to compute the propagation and detection of signals. It is simple and eliminates the complicated timing issue during test generation for the crosstalk fault in the conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show that the described test generation procedure is effective in generating test patterns for this scheme.
Next, a BIST scheme based on a squarewave test signal to test also the induced-glitch type of the crosstalk fault of embedded circuits of SoC in the boundary scan environment for deep sub-micron VLSI is proposed. The scheme applies squarewave test signals in conjunction with pseudo random patterns to induce glitches which are caused by crosstalk faults and tests them. Modifications on boundary scan cells with simple added detection circuits to facilitate this test scheme are presented. Experimental results show that the average fault coverage obtained by applying the scheme to large size benchmark circuits can easily reach 90%.
Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a pulse of specified width, CWP, to the victim line and detects the propagation of the CWP at the output of the victim line to detect the existence of crosstalk faults. Experimental results show that the detection quality is high when no time skew at test signals and no process variation on interconnects occurs. The scheme is simple and is considered effective in detecting crosstalk faults.
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author2 |
Chung Len Lee |
author_facet |
Chung Len Lee Ming-Shae Wu 吳明學 |
author |
Ming-Shae Wu 吳明學 |
spellingShingle |
Ming-Shae Wu 吳明學 VLSI Crosstalk Fault Testing with Oscillation Signals |
author_sort |
Ming-Shae Wu |
title |
VLSI Crosstalk Fault Testing with Oscillation Signals |
title_short |
VLSI Crosstalk Fault Testing with Oscillation Signals |
title_full |
VLSI Crosstalk Fault Testing with Oscillation Signals |
title_fullStr |
VLSI Crosstalk Fault Testing with Oscillation Signals |
title_full_unstemmed |
VLSI Crosstalk Fault Testing with Oscillation Signals |
title_sort |
vlsi crosstalk fault testing with oscillation signals |
publishDate |
2006 |
url |
http://ndltd.ncl.edu.tw/handle/12782483001913698645 |
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