| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 94 === H.264/AVC is the new video coding standard of ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MEPG). H.264 is most popular video standard due to high compress rate and better quality. In particular, the baseline profile of H.264/AVC has been accomplished progressively. In recently year, digital TV is widely adopted so that H.264’s Main Profile focus on quality of video will be attended gradually. Therefore, the improvement of resolution and quality for large frame will become important issue. Motion compensation always is important module and kernel of system in video standard. For enhancing quality of video, H.264’s main profile adopts new features such as Bi-prediction, weighted prediction and direct mode coding. In this thesis, a bandwidth-efficient motion compensation system is proposed for high definition resolution supported by main profile in H.264/AVC. Presently, we provide a novel structure of motion compensation system in main profile to improve system throughput. Furthermore, we propose Combined Luma/Chroma interpolator architecture in motion compensation and a novel data-reuse technique: Ectended-2D Column Major Approach. Both Luma and Chroma MB can be interpolated by combined Luma/Chroma interpolator. A combined Luma/Chroma interpolator is proposed in order to save area, which achieves approximately 44% cost reduction. Additionally, an Extend-2D column major approach is presented, which improves 50% ~ 60% required bandwidth within decoder.
The video decoder should deal with large amount of data from external memory due to a real-time high-quality decoding demand. Therefore, both limited access time and bandwidth of memory access on BUS is bottleneck of entire video decoder. However, general memory controller may be not design for multimedia applications. In this thesis, the bandwidth-efficient memory controller architecture is proposed for H.264 decoder to increase limited bandwidth over external bus. The memory controller can support all module of H.264 decoder such as motion compensation and de-blocking filter, etc. Besides, the multiple reference pictures technique can be supported by our proposed memory controller, and can employ unique memory to store all required data for video decoder. About simulation results, the bus utilization can be improved up to 90% for our proposed memory controller. The bandwidth of memory access may be improved to 50% ~ 60% for entire video decoder adopting our proposed bandwidth-efficient motion compensation memory organization. Finally, the system throughput that is proposed by our proposed architecture can meet with specification with HDTV standard at high bit-rate.
|
|---|
