Architecture and Performance of a Satellite Transponder with On-Board Processing Capability
碩士 === 國立交通大學 === 電信工程系所 === 94 === We consider a secure satellite link in which a slow frequency-hopped (FH), turbo-coded DPSK signal is used in the uplink. Several detector structures are proposed and both processing and bent-pipe transponders are considered although our emphasis is on the former...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09618115000829453504 |
| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 94 === We consider a secure satellite link in which a slow frequency-hopped (FH), turbo-coded DPSK signal is used in the uplink. Several detector structures are proposed and both processing and bent-pipe transponders are considered although our emphasis is on the former class. Regarding the turbo-coded DPSK signal as an equivalent serially concatenated coding scheme with the inner code being the rate-1 DPSK encoder, we propose an iterative decoder architecture and examine the effectiveness of different decoding schedules. We also consider two interleaver
structures for the corresponding turbo codes. The first one is a conventional block oriented interleaver while the second one is the so-called inter-block permutation (IBP) interleaver. Numerical results indicate that sufficient AJ margin is achievable with the proposed signal waveform and decoding scheme. Furthermore, the IBP-interleaved turbo coded system offer additional tradeoff between hopping rate and performance. It offers sufficient AJ capability even the FH rate is relatively low.
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