| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 94 === Wireless and mobile communications is one of the fast growing microelectronics applications. Traditionally, the RFICs are implemented in GaAs or SiGe process. With the progress of scaled down CMOS technology, RFICs can be implemented in CMOS process and provide high integration and low cost. Under reduced supply voltages, many circuit topologies of the RF front-end can not meet the stringent dynamic range of wireless receiver. It needs more efforts toward finding out new topology suitable to operate at sub-1V supply voltage.
In this thesis, we analyze the design of low-voltage folded-switching mixer and employee it to the proposed low-IF receiver RF front-end. The new mixer has high voltage gain (8.99dB), moderate noise figure (10.3dB in simulation), moderate linearity (P1dB = -9dBm, IIP3 = 4dBm), and low power consumption (2.87mW). The total chip size is 1.24 × 1.19 mm2. This chip is designed and implemented in CMOS 0.18-μm 1P6M technology and measured in National Chip Implementation Center (CIC).
|
|---|
