Study of N-type LTPS TFTs Degradation Under Gate Pulse Stress

• Main Authors: Chien-Kun Chen, 陳建焜
• Other Authors: Ya-Hsiang Tai
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/51027282893763574472

碩士 === 國立交通大學 === 顯示科技研究所 === 94 === Polycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode (AMOLED) displays. The significant advantages over amorphous silicon (a-Si) TFTs are in the higher current driving capability and the better reliability. In poly-Si TFT-controlled displays, poly-Si TFTs are used to implement pixel circuits and driving circuits on a single glass substrate to reduce system cost and posses compact module. Therefore, the poly-Si TFT is the best candidate to realize system–on–panel (SOP). However, unlike pixel TFTs, TFTs in driver circuits are subjected to high-frequency voltage pulses. Therefore, the degradation mechanism under dynamic operation should be understood in detail. In this thesis, the device degradation of low-temperature polycrystalline thin film transistor under AC stress has been investigated. The degree of degradation is concerned with the magnitude of the lateral transient electrical field and the variation of the number of the carriers near the source/drain. For the gate voltage swing of -15V to 15V, it is observed that the degradation depends on the falling time of the gate pulse but does not depend on the rising time. However, it is firstly observed that the degradation is both dependent of rising time and falling time if the voltage swings below the threshold voltage. TFT’s slicing model take channel resistance and oxide capacitance into consideration is proposed to explain the degradation of poly-Si TFTs under Gate Pulse Stress. A reasonable agreement between the experiment data and the simulation results reveals that the degradation is related to the transient electrical field and the various amount of the charge near the edges of the channel. In addition, a new index which can be simulated using a slicing model is proposed and it is almost proportional to the degradation degree. For the peripheral circuit in poly-Si panel, NAND and NOR logic gates are the fundamental elements. When input terminals A and B of NAND and NOR are 0 and 1, respectively, floating drain TFTs appear. Therefore, a new AC stress condition is needed to discuss, called floating drain AC stress. We will also discuss the phenomenon for poly-Si TFT under floating drain AC stress in the chapter 3.