Design and Implementation of Multi-Giga Bit Parallel Adaptive Decision Feedback Equalizer

• Main Authors: Chi-Shiung Lin, 林志雄
• Other Authors: Shyh-Jye Jou
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/36653261716961171331

碩士 === 國立中央大學 === 電機工程研究所 === 94 === Internet and data transmission technique are going to grow fast, the trend of recent Ethernet system will make a high effort to provide high data rate services. According to the related standard about high speed wire-lined communication system, the data rate is more than gigabits per second, even several gigabits per second. Hence, for the high transmitted data rate, the Inter-Symbol Interference (ISI) effect always exists, and it is serious and dominant for the signal distortion. The design of Adaptive Decision Feedback Equalizer (ADFE) is very important because it determines the system performance, such as Bit Error Rate (BER) and data rate. The computation cost of ADFE is also large for hardware implementation. The conventional ADFE and the Least-Mean-Square (LMS) algorithm inherently have feedback inside the data flow and the operating frequency is limited by the feedback structures. The internal feedback or recursive in the architecture algorithms makes it difficult to implement systems concurrency in the form of either pipelined or paralleled processing. This thesis provides a high speed equalizer design, and it is suitable for the 10GBase-LX4 Ethernet system in IEEE 802.3ae standard (IEEE 802.3ae Ad-hoc database). We design and implement an all digital 3.5Gbps blind ADFE based on the TSMC 0.13 μm CMOS technology. The implementation shows that the chip area is 1.55 × 1.55 mm2 with operation up to 3.5 Gbps using 1.2-V supply and dissipates 110 mW.